Part of the Physical Sciences and Mathematics Commons
FPGA Implementation of Parallel Adder Using Reversible Logic Gates, S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran, K. Umapathy Karthikeyan Umapathy
Enhanced Spanning-Tree Adder Structures Using Carry Increment Adders, D. Muthukumaran, K. Umapathy, S. A. Yuvaraj, K. Gunasekaran Karthikeyan Umapathy
FPGA Based Implementation of Hamming Encoder and Decoder, K. Umapathy, S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran Karthikeyan Umapathy
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