FPGA Implementation of Parallel Adder Using Reversible Logic Gates, S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran, K. Umapathy
Karthikeyan Umapathy

Enhanced Spanning-Tree Adder Structures Using Carry Increment Adders, D. Muthukumaran, K. Umapathy, S. A. Yuvaraj, K. Gunasekaran
Karthikeyan Umapathy

FPGA Based Implementation of Hamming Encoder and Decoder, K. Umapathy, S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran
Karthikeyan Umapathy