FPGA Implementation of Parallel Adder Using Reversible Logic Gates, S. A. Yuvaraj, K. Gunasekaran, D. Muthukumaran, K. Umapathy
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Enhanced Spanning-Tree Adder Structures Using Carry Increment Adders, D. Muthukumaran, K. Umapathy, S. A. Yuvaraj, K. Gunasekaran
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