Performance analysis of system-on-chip architectures for ultrasonic data compression
Ultrasonic NDE and imaging applications utilize a large amount of information. Most of these applications demand real-time data processing with low power consumption. Compression of the collected ultrasonic data helps to reduce the storage, as well as rapid data transmission to remote locations for expert analysis. The objective of this study is to develop embedded system-on-chip architectures for ultrasonic data compression, and analyze the performance of different design methods according to the application requirements. The system is implemented using Xilinx Zynq System-on-Chip (SoC), which combines both ARM processor and field-programmable gate array (FPGA) on the same chip. The major parameters analyzed in this study are signal fidelity, hardware resource utilization and computational processing speed. The hardware and software co-design implementation is about five times faster compared to software only implementation using Zynq SoC.
IEEE International Ultrasonics Symposium, IUS
Digital Object Identifier (DOI)
Boyang Wang, Pramod Govindan, & Jafar Saniie. (2016). Performance analysis of system-on-chip architectures for ultrasonic data compression. The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, 7728507. 10.1109/ULTSYM.2016.7728507