Title

Performance analysis of system-on-chip architectures for ultrasonic data compression

Document Type

Conference Proceeding

Publication Date

11-1-2016

Subject Area

ARRAY(0x55ab97fb4e08)

Abstract

Ultrasonic NDE and imaging applications utilize a large amount of information. Most of these applications demand real-time data processing with low power consumption. Compression of the collected ultrasonic data helps to reduce the storage, as well as rapid data transmission to remote locations for expert analysis. The objective of this study is to develop embedded system-on-chip architectures for ultrasonic data compression, and analyze the performance of different design methods according to the application requirements. The system is implemented using Xilinx Zynq System-on-Chip (SoC), which combines both ARM processor and field-programmable gate array (FPGA) on the same chip. The major parameters analyzed in this study are signal fidelity, hardware resource utilization and computational processing speed. The hardware and software co-design implementation is about five times faster compared to software only implementation using Zynq SoC.

Publication Title

IEEE International Ultrasonics Symposium, IUS

Volume

2016-November

Digital Object Identifier (DOI)

10.1109/ULTSYM.2016.7728507

ISSN

19485719

E-ISSN

19485727

ISBN

9781467398978

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